Quadric in the news.
(January 19, 2026) EE Times – Quadric has raised a $30M Series C as it looks to grow its team. The Silicon Valley startup has raised $72M to date, was profitable for the previous two quarters, and more than doubled its pre-money valuation from the last round.
(July 17, 2025) Semiconductor Engineering – Is a 1024-bit DSP really the solution you want in your next chip as you fight the evolving AI battle? Or would you want a Crocodile Dundee-sized DSP solution? Quadric's Chimera architecture is unique in crafting building blocks placing small tiles of MACs immediately adjacent to a full-fledged, programmable 32-bit ALU.
(July 7, 2025) Market Research Future – Quadric's collaboration with DENSO marks a pivotal shift in DENSO's direction towards developing automotive semiconductor technology. With Quadric's focus on high-performing edge processing, DENSO can create semiconductor solutions that meet the rising computational needs of modern automobiles.
(July 1, 2025) EE Times – For the second year in a row, Quadric ranked in the top 100 silicon startups. Founded in 2016, Quadric.io is a semiconductor IP company specializing in optimized machine-learning processors for on-device AI inference.
(June 12, 2025) Semiconductor Engineering – RISC-V is simply just another control CPU in the same vein as the Arm, x86, MIPS, Xtensa and ARC processors. The latter two also provide the designer with instruction set customization ability similar to, and superior to, that of RISC-V.
(June 12, 2025) Semiconductor Engineering – We've not seen any planned uses of HBM outside of the data center — not even the high-end automotive market. Car companies building high-end SAE Level 4 automated driver-assistance systems (ADAS) want silicon solutions that are air-cooled and cost less than four figures.
(June 11, 2025) SemiWiki – The Chimera GPNPU from Quadric runs all AI/ML graph structures. The revolutionary Chimera GPNPU processor integrates fully programmable 32bit ALUs with systolic-array style matrix engines in a fine-grained architecture. Up to 1024 ALUs in a single core, with only one instruction fetch and one AXI data port.
(June 4, 2025) Semiconductor Engineering – We're speaking with auto OEMs who are talking about putting three petaOPS of compute in a car for real L5. That used to be a supercomputer 5 or 10 years ago. By 2035 you may be driving that thing. So it's all about scale, system, and specialization.
(May 21, 2025) Semiconductor Engineering – Clearly, in data centers and automotive, along with some other segments, people are trying to do 20 TOPS in the base and modularly add on 100. How do I make that happen? If you have multiple chips and spread the execution of a model over two or three different chips that are modularly added on, all are going into memory.
(May 15, 2025) Semiconductor Engineering – People are looking at flexibility and scalability. There are a heck of a lot of systems and applications where companies want to build base-model silicon with the bare minimum amount of AI they need, and some ability to scale up, whether it be a second chip or a chiplet.
